1. Field of the Invention
The present invention relates to a semiconductor device including an insulated gate bipolar transistor (IGBT) and a free wheel diode (hereafter, diode) in one chip. The present invention also relates to a method of manufacturing a semiconductor device in which an IGBT and a diode are formed in one chip.
2. Description of the Related Art
In a conventional semiconductor chip including an IGBT and a diode in one chip, an N+ type layer operating as a cathode layer is formed in a diode forming region and a P+ type layer operating as a collector layer is formed in an IGBT forming region as described, for example, in US 2005/0017290 A (corresponding to JP-A-2005-57235). In a process of manufacturing the semiconductor device having the above-described structure, a crack may generate when the semiconductor device is handled in a thin-film state. An exemplary process of manufacturing a conventional semiconductor device, in which an IGBT and a diode are integrated, will be described with reference to FIG. 35A to FIG. 36D.
During a process illustrated in FIG. 35A, an N type semiconductor substrate J1 is prepared. The N type semiconductor substrate J1 has a thickness of greater than or equal to 200 μm and is not warped. The N type semiconductor substrate J1 is, for example, a FZ substrate. After forming an oxide layer J2 on a main surface of the N type semiconductor substrate J1, openings are provided at predetermined portions of the oxide layer J2 by a pattern forming process. Then, P type impurities are implanted through the openings in the oxide layer J2 so as to form a P type diffusion layer J3 and a P type guard ring layer J2 in an outer peripheral section. The openings also function as alignment targets during the subsequent patterning process.
During a process illustrated in FIG. 35B, a P type base region J5 is formed. Then, a trench gate structure J6 is formed in an IGBT forming region and a gate wire J7 and an emitter electrode J8 are formed so as to provide a metal oxide semiconductor (MOS) device.
During a process illustrated in FIG. 35C, a main surface of the N type semiconductor substrate J1, that is, a surface of the N type semiconductor substrate J1 on which the MOS device is formed, is attached on a support base J10, for example, through an adhesive. During a process illustrated in FIG. 35D, a thickness of the N type semiconductor substrate J1 is reduced to a predetermined thickness from a rear surface of the N type semiconductor substrate J1. Although the thickness of the N type semiconductor substrate J1 is reduced during the above-described process, the N type semiconductor substrate J1 is not handled in a thin-film state because the N type semiconductor substrate J1 is attached to the support base J10. In the above-described process, the thickness of the N type semiconductor substrate J1 may be reduced, for example, by a grinding process or a wet etching process. When the thickness of the N type semiconductor substrate J1 is reduced by a grinding process, large amount of particles may generate.
During a process illustrated in FIG. 36A, N type impurities are implanted from the rear-surface side of the N type semiconductor substrate J1. During a process illustrated in FIG. 36B, a mask is disposed on the rear surface of the N type semiconductor substrate J1. Openings are provided at predetermined portions of the mask by a pattern forming process, and P type impurities are implanted through the openings. Another mask is disposed on the rear surface of the N type semiconductor substrate J1. Openings are provided at predetermined portions of the mask by a pattern forming process, and N type impurities are implanted through the openings. Then, an anneal treatment is performed so that a field stop (FS) layer J11, a P++ type collector layer J12, and an N++ type cathode layer (first conductivity type layer) J13 are formed.
During a process illustrated in FIG. 36C, a rear-surface electrode J14 being in contact with the P++ type collector layer J12 and the N++ type cathode layer J13 is formed. During a process illustrated in FIG. 36D, the support base J10 is separated from the N type semiconductor substrate J10. In the above-described way, the semiconductor device including the IGBT and the diode in one chip is manufactured.
In the above-described manufacturing method, the P++ type collector layer J12 and the N++ type cathode layer J13 as well as the FS layer J11 are formed after forming the MOS device at the main-surface side of the N type semiconductor substrate J12. Thus, the anneal treatment performed after implanting the N type impurities or the P type impurities is limited to a laser anneal. A protective layer and a wiring structure are formed at the main-surface side of the N type semiconductor substrate J1. For example, an upper temperature limit of a protective layer made of polyimide is about 350° C., and an upper temperature limit of a wiring structure made of aluminum is about 490° C., and an upper temperature limit of an adhesive layer of the support base J10 is about 200° C. Thus, an anneal treatment that increases a temperature of the whole substrate cannot be performed, and only a laser anneal that increases a temperature of the rear surface locally can be performed.
The laser anneal is an instantaneous anneal. The laser anneal can activate the implanted impurities, but the laser anneal cannot diffuse the impurities. Thus, a leakage is likely to occur. In particular, in a case where the thickness of the N type semiconductor substrate J1 is reduced by a grinding process, large amount of particles may generate, and the particles may block the implanted impurities. Thus, a deficiency may generate at the P++ type collector layer J12 and the N++ type cathode layer J13, and a leakage is more likely to occur.
When the mask for forming the P++ type collector layer J12 or the N++ type cathode layer J13 is pattern formed, an insulating layer formed on the main surface, for example, a gate oxide layer in the trench gate structure is used as an alignment key. Thus, a relative position of the P++ type collector layer J12 and the N++ type cathode layer J13 may be misaligned. For example, a distance between the P++ type collector layer J12 and the N++ type cathode layer J13 may be longer than a predetermined distance, or the P++ type collector layer J12 and the N++ type cathode layer J13 may overlap.
In order to prevent an exhaustion of holes at a recovery, a P type layer may be partially formed in an N type layer that operates as a cathode layer. Also in this case, a forming position of the P type layer may be out of a predetermined position.